Movidius Neural Compute Stick (Intel)

Provider: Intel
Platform: Neural compute stick
Web: https://developer.movidius.com/
Contact: Finian G Rogers
E-mail: finian.g.rogers@intel.com
 

The Movidius™ Neural Compute Stick is a new device for developing and deploying deep learning algorithms at the edge. Movidius created the Neural Compute Stick (NCS) to make deep learning application development on specialized hardware even more widely available.

The NCS is powered by the same low-power Movidius Vision Processing Unit (VPU) that can be found in millions of smart security cameras, gesture-controlled autonomous drones, and industrial machine vision equipment, for example. The convenient USB stick form factor makes it easier for developers to create, optimize and deploy advanced computer vision intelligence across a range of devices at the edge.

The USB form factor easily attaches to existing hosts and prototyping platforms, while the VPU inside provides machine learning on a low-power deep learning inference engine. You start using the NCS with trained Caffe framework-based feed-forward Convolutional Neural Network (CNN), or you can choose one of our example pre-trained networks. Then, by using our Toolkit, you can profile the neural network, then compile a tuned version ready for embedded deployment using our Neural Compute Platform API.

Here are some of its key features:

  • Supports CNN profiling, prototyping, and tuning workflow
  • All data and power provided over a single USB Type A port
    Real-time, on device inference – cloud connectivity not required
  • Run multiple devices on the same platform to scale performance
  • Quickly deploy existing CNN models or uniquely trained networks

At the Intel Movidius team, we’re inspired by the incredible sophistication of the human brain’s visual system, and I’d like to think we’re getting a little closer to matching its capabilities with our new Neural Compute Stick.
To get started, you can visit developer.movidius.com for more info – let us know what you think by dropping feedback on the @movidius channel. The Movidius Neural Compute Toolkit takes offline deep learning inference applications deployment to places never gone before.

For more information:

Webinar:

Integrated and Open Development Platform (AVL)

Provider: AVL
Platform: Integrated and Open Development Platform for CPS
Web: https://www.avl.com/integrated-open-development-platform
Contact: Eric Armengaud
E-mail: eric.armengaud@avl.com

Integrated and Open Development Platform

This components platform from AVL supports the entire development process for road vehicles from office to lab to road by integrating real (hardware) and virtual (simulation models) development methods into one framework: Such an integrated development platform offers a seamless exchange of data from the concept phase to road testing. Thereby, the characteristic operating conditions like legislative test cycles, real world driving emissions and customer specific drive profiles or misuse tests can all be applied in a real as well as in a virtual environment during all phases of development.

This also includes a cross-phase usage of tools like automatic optimization and calibration. This approach facilitates an efficient and goal-oriented development and validation of extremely complex drive configurations. Benefits for the researchers and engineers: Test cases and development tasks can be performed with a plant model of the entire vehicle, independently of the availability of hardware components in every stage of the development process.

Specific features are:

  • Interfaces for a wide variety of simulation tools used for vehicle development and control
  • Support of FMI (Functional Mock-up Interface)
  • Link to PLM systems and data bases

In FED4SAE, AVL will support SMEs to foster their products based on AVL tools and platforms. Within this framework, different tools can connect on and exchange product-related information over the tool boundaries by means of well-defined mechanisms. The control logics and the diagnostic procedures can be implemented and tested on dedicated SW and Hardware-in-the-loop features.

For more information, see: https://www.avl.com/integrated-and-open-development-platform

TIME4SYS (Thales)

Provider: Thales
Platform: TIME4SYS
Web: https://www.polarsys.org/projects/polarsys.time4sys
Contacts: Rafik Henia
Laurent Rioux
E-mail: rafik.henia@thalesgroup.com
laurent.rioux@thalesgroup.com

TIME4SYS Platform

Context

Usually, the industrial practices rely on the subjective judgment of experienced software architects and developers to predict how design decisions may impact the timing behavior of real-time embedded systems. This is however risky since eventual timing errors are only detected after implementation and integration, when the software execution can be tested on system level, under realistic conditions. At this stage, timing errors may be very costly and time consuming to correct. Therefore, to overcome this problem there is a need for efficient, reliable and automated timing estimation methods applicable already at early design stages and continuing throughout the whole development cycle.

Introducing timing verification activities into the design process of real-time embedded systems has always been a challenge as the inputs required for the verification, in particular the worst-case execution time and the system behavior description, are moving target all across the different design phases. Thanks to the introduction of model based methods (in particular viewpoints for non-functional properties) in the industrial development process [4], this goal seems to be reachable for model-based verification techniques, such as simulation, scheduling analysis or model-checking. Starting from very high level system architecture and rough timing allocations, the model-based timing verification has to be refined at each step of the project (architectural design, detailed design, coding, unit test and software validation phases) down to concrete timing measurements on the final system. A major problem however persists: model-based timing verification techniques are often not directly applicable to conceptual design due to the semantic gaps between their respective models. Solving this issue is essential to break the remaining walls separating model-based timing verification from the development process of real-time embedded systems, and to enable its use in the industry.

PolarSys Time4Sys

PolarSys Time4Sys is a timing performance framework that fills the semantic gaps between the design models of real-time systems and the models of timing verification tools. Time4Sys is composed of two building blocks (the Design and the Verification pivot models) as well as a set of transformation rules between them. Both pivot models are based on the Time4Sys meta-model.

Time4Sys uses a subset of the MARTE OMG standard [7] as a basis to represent a synthetic view of the system design model that captures all elements, data and properties impacting the system timing behavior and required to perform timing verification (e.g. tasks mapping on processors, communication links, execution times, scheduling parameters, etc.). Time4Sys is not limited to the use of a particular design modeling tool and environment. It can be connected to various environments and languages such as UML, SysML [6], AADL [5], or any other proprietary environment (e.g. Capella).

Figure 1: Bridging the gap between design tools and verification tools

Scheduling analysis and simulation are seldom directly applicable to the conceptual design models in general and to Time4Sys Design models in particular due to the semantic mismatch between the latter and the variety of analysis and simulation models known from the classical real time systems research and represented by academic and commercial tools. Transformation rules are therefore required to generate a Time4Sys Verification model preserving the timing behavior modeled in the corresponding Time4Sys Design model, while ensuring the compatibility with the variety of existing timing verification tools. After timing verification in the selected tool, results are injected in Time4Sys Verification model. Then, they are translated to be compliant with the original design model and injected back in Time4Sys Design.

Time4Sys Architecture

By using MDE settings, Time4Sys is being developed as an Eclipse Polarsys plugin. Time4Sys proposes four capabilities: modeling and viewing the Time4sys model, A dedicated meta-model based on the MARTE standard (available for download), model transformations able to transform and adapt Time4sys model for verifications tool and connectors to import/export models from design tools and verifications tools.

Figure 2: Time4Sys Platform architecture

Time4Sys meta-models:

The Time4Sys framework is composed by 4 Meta-models:

  • The MARTE meta-model which implement the MARTE standard Language to capture all concepts related to model real-time software and embedded hardware.
  • The Design Meta-model which extends the MARTE meta-model with missing concepts need to model the design model of the application and to model the verification model.
  • The Results meta-model contains all concepts required to model various results produced by verification tools and need to be provided to the design architects.
  • The Trace Meta-model contains concepts to model traces to model Gantt charts and execution traces.

Time4Sys graphical editor:

The graphical editor for the Time4Sys models is a java module based on Sirius [8]. It offers the capabilities to edit and view Time4Sys models via a graphical user interface. This module also offers menus to apply model transformations rules and launch the appropriate verification tool (Pegase [3], MAST [1], Cheddar [2] and in the future ROMEO [9]). The next Figure shows the graphical interface for this editor.

Figure 3: Time4sys model editor

Time4sys model transformations rules:

The transformations rules aim to transform Time4sys model into another time4sys model by solving semantic gaps for verification tools. Time4sys proposes a set of transformations rules which can be assembled together to solve the semantic gaps between design models and verification tool models.

Time4sys connectors:

A connector is able to bridge the Time4sys framework to a design tool, a verification tool or a visualization tool. Time4sys is provided with connectors able to import/export Time4sys model to Pegase Tool [3], MAST [1] and Cheddar [2] (ongoing). ROMEO [9] connector is currently in under study. A prototype of the connector to the design tool Capella [10] will be also provided.

Note: The MARTE meta-model can be downloaded as a separate and independent package. Time4sys aims to be the official repository for the MARTE meta-model.

System documentation:

Available at https://polarsys.org/time4sys/documentation/

References

[1] MAST, “Modeling and analysis suite for real-time applications,”http://mast.unican.es/

[2] “The cheddar project: a gpl real-time scheduling analyzer,” http://beru.univ-brest.fr/ singhoff/cheddar/

[3] RTaW-Pegase, “Modeling, simulation, and timing analysis for communication networks,” http://www.realtimeatwork.com/software/rtawpegase/.

[4] K. Balasubramanian, A. S. Krishna, E. Turkay, J. Balasubramanian, J. Parsons, A. S. Gokhale, and D. C. Schmidt, “Applying model-driven development to distributed real-time and embedded avionics systems,” IJES, vol. 2, no. 3/4, pp. 142–155, 2006.

[5] AADL, “Architecture analysis and design language,” http://www.aadl.info/aadl/currentsite/

[6] SysML, “Systems modeling language,” http://www.omg.org/spec/SysML

[7] MARTE, “Modeling and analysis of real-time and embedded systems,” http://www.omg.org/omgmarte/

[8] SIRIUS, Sirius enables the specification of a modeling workbench in terms of graphical, table or tree editors with validation rules and actions using declarative descriptions. https://www.polarsys.org/eclipse/sirius

[9] ROMEO, D. Lime, O. H. Roux, C. Seidner, and L.-M. Traonouez. Romeo: A parametric model-checker for Petri nets with stopwatches. In TACAS, volume 5505 of Lecture Notes in Computer Science, pages 54–57. Springer, 2009. http://romeo.rts-software.org/

[10] CAPELLA: a model-based system engineering tool and methodology, https://polarsys.org/capella/

Compute Card (Intel)

Provider: Intel
Platform: Compute card
Web: https://www.intel.com/content/www/us/en/compute-card/intel-compute-card.html
Contact: Finian G Rogers
E-mail: finian.g.rogers@intel.com
 

Imagine a tiny computer found in unexpected places across the city—making your daily life richer, more informed, and easier. That’s the Intel® Compute Card. Revolutionary in size, form, and function, the Compute Card is driving the future of smart computing, turning your world into an enhanced, connected one.

Intel unveiled the Intel® Compute Card, a modular platform developed to transform how devices compute and connect. It has all of the elements of a full computer, including Intel SoC, memory, storage and wireless connectivity with flexible I/O options so that hardware manufactueres can optimise for particular solutions.

At Computex 2017, Intel showcased a variety of solutions utilizing the Intel Compute Card that are currently being developed by a wide range of partners, spanning laptops and tablets to digital signage and POS to AIOs and intelligent whiteboards.

Intel also released the Compute Card Device Design Kit, a set of guides and reference designs that contain the information a device developer will need to create a product that supports an Intel Compute Card.

For more information:

Overview video:

WESU PLATFORM and X-Nucleo expansion boards (STM)

Provider: STM Italy
Platform: WeSU PLATFORM and X-Nucleo expansion boards
Web: WeSU
STM32 Nucleo Expansion Boards
Contact: Antonio Lionetto
E-mail: antonio.lionetto@st.com

What is WESU?

WeSU is a System Evaluation Board designed to provide a cost effective solution for precise motion sensing in wearable and embeddable object motion applications.

The connectivity granted by the best in class BlueNRG and supported by the integrated balun permit to maximize the RF performances with low area occupancy and design effort. Android or iOS APP can be used for displaying information sent by the WeSU through BLE Connectivity as well as for setting operative modes. Compliance to the Bluetooth (BLE 4.0) stack specification allows to expose application functionalities through structured services and characteristics in which WeSU is hosting a GATT (Generic Attribute) Server while mobile app is acting as a GATT client.

X-Nucleo Expansion Boards

STM32 Open Development Environment is a fast and affordable way to develop and prototype innovative devices and applications with state-of-the-art ST components leveraging these in a comprehensive set of functions for connectivity, power, audio, motor control and more in a shape of stackable expansion boards (X-NUCLEO) and open software environment designed around the STM32 microcontroller family.

The combination of a broad range of expandable boards based on leading-edge commercial products and modular software, from driver to application level, enables fast prototyping of ideas that can be smoothly transformed into final designs. In this FED4SAE project ST-Italy intends to promote CPS and IoT applications that may utilise not only BLE communication, Motion MEMS, Environmental sensing extension boards, but also an entire portfolio will be available to the selected Application Experiments.

For further information on WeSu please go here.
For information on ODE- STM32 Nucleo expansion boards please go here.

STM32 Platform (STM)

STM32 PLATFORM

These platforms are based on the STM32 processor family. The STM32 family of 32-bit Flash microcontrollers based on the ARM Cortex™-M processor is designed to offer new degrees of freedom to MCU (Microcontroller) users.

It offers a 32-bit product range that combines high performance, real-time capabilities, digital signal processing, and low-power, low-voltage operation, while maintaining full integration and ease of development. The unparalleled and large range of STM32 devices, based on an industry-standard core and accompanied by a vast choice of tools and software, makes this family of products the ideal choice, both for small projects and for entire platform decisions. To support this family of processors a large number of evaluation and development boards is available.

These boards are available either from ST-F or other partners from the STM32 ecosystem.


The STM32 platform can address the following application domains: automation (e.g. Human Machine Interface, Programmable Logic Controller, power management solution for industrial-Robotics or Mobile-Robotics), building technology (e.g. control heating ventilation and air conditioning systems, lights, shutters, gates, doors, appliances, security and surveillance systems…), communications and networking (e.g. systems assuring more efficient, faster and more secure solutions for voice, data and multimedia streams, based on IP and other protocols), healthcare and wellness (e.g. clinical diagnostic and therapy, medical imaging…), home appliances and power tools (e.g. motor control subsystems), and transportation (car body electronics, active and passive safety systems, steering and chassis solutions including electric steering, adaptive damper management, energy recovery in electric vehicles).

For More information on the STM32 Family

STM32 32-bit ARM Cortex MCUs: http://www.st.com/en/microcontrollers/stm32-32-bit-arm-cortex-mcus.html
Microcontrollers: http://www.st.com/en/microcontrollers.html